A hardware-implementation-friendly pulse-coupled neural network algorithm for analog image-feature-generation circuits

Pulse-coupled neural networks (PCNNs) are biologically inspired algorithms that have been shown to be highly effective for image feature generation. However, conventional PCNNs are software-oriented algorithms that are too complicated to implement as very- large-scale integration (VLSI) hardware. To employ PCNNs in image-feature-generation VLSIs, a hardware- implementation -friendly PCNN is proposed here. By introducing the concepts of exponentially decaying output and a one-branch dendritic tree, the new PCNN eliminates the large number of convolution operators and floating-point multipliers in conventional PCNNs without compromising its performance at image feature generation. As an analog VLSI implementation of the new PCNN, an image-feature-generation circuit is proposed. By employing floating-gate metal-oxide-semiconductor (MOS) technology, the circuit achieves a full voltage-mode implementation of the PCNN in a compact structure. Inheriting the merits of the PCNN, the circuit is capable of generating rotation -independent and translation-independent features for input patterns, which has been verified by SPICE simulation.