Preparation of solder bumps incorporating electroless nickel-boron deposit and investigation on the interfacial interaction behaviour and wetting kinetics

被引:20
作者
Lee, CY [1 ]
Lin, KL [1 ]
机构
[1] Natl Cheng Kung Univ, Dept Mat Sci & Engn, Tainan 701, Taiwan
关键词
D O I
10.1023/A:1018599609177
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Investigation of a method for preparing solder bumps on Al pads incorporating electroless nickel deposition and soldering for solder bumps was undertaken. The experimental variables included bath temperature and dipping velocity. The formation of intermetallic compounds and wetting kinetics between electroless Ni-B deposit and molten solder was also investigated. The interfacial interaction behaviour was studied with the aid of Auger depth profile and scanning electron microscopy. Intermetallic compounds Ni3Sn4 and Ni3Sn2 were formed between the Ni-B deposit and solder. Aluminium atoms diffuse through the intermetallic compound layer and dissolve in the solder when the electroless Ni-B deposit is entirely consumed. The contact angles of molten solder on a Ni-B deposit, measured with the sessile drop method, decrease with increasing temperature and time. The activation energy for wetting of molten solder on a Ni-B deposit was estimated to be 208.27 kcal mol(-1).
引用
收藏
页码:377 / 383
页数:7
相关论文
共 42 条
[1]  
BASHFORTH F, 1982, ATTEMPT TEST THEORY, V1, P151
[2]   COST PERFORMANCE SINGLE-CHIP MODULE [J].
BENDZ, DJ ;
GEDNEY, RW ;
RASILE, J .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1982, 26 (03) :278-285
[3]  
BRADY MJ, 1989, REV SCI INSTRUM, V56, P1459
[4]   NICKEL PLATING ON STEEL BY CHEMICAL REDUCTION [J].
BRENNER, A ;
RIDDELL, GE .
JOURNAL OF RESEARCH OF THE NATIONAL BUREAU OF STANDARDS, 1946, 37 (01) :31-34
[5]   SOLID LOGIC TECHNOLOGY - VERSATILE HIGH-PERFORMANCE MICROELECTRONICS [J].
DAVIS, EM ;
HARDING, WE ;
SCHWARTZ, RS ;
CORNING, JJ .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1964, 8 (02) :102-&
[6]  
De Haven P. E., 1985, MATER RES SOC S P, V40, P123
[7]   SELECTIVE ELECTROLESS NI-CU(P) DEPOSITION FOR VIA HOLE FILLING AND CONDUCTOR PATTERN CLADDING IN VLSI MULTILEVEL INTERCONNECTION STRUCTURES [J].
DUBIN, VM .
JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1992, 139 (02) :633-638
[8]   CALCULATION OF SOLID-LIQUID-VAPOR CONTACT ANGLES FOR BINARY METALLIC SYSTEMS [J].
EUSTATHOPOULOS, N ;
PIQUE, D .
SCRIPTA METALLURGICA, 1980, 14 (12) :1291-1296
[9]   A VLSI BIPOLAR METALLIZATION DESIGN WITH 3-LEVEL WIRING AND AREA ARRAY SOLDER CONNECTIONS [J].
FRIED, LJ ;
HAVAS, J ;
LECHATON, JS ;
LOGAN, JS ;
PAAL, G ;
TOTTA, PA .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1982, 26 (03) :362-371
[10]   LEAD-INDIUM FOR CONTROLLED-COLLAPSE CHIP JOINING [J].
GOLDMANN, LS ;
HERDZIK, RD ;
KOOPMAN, NG ;
MARCOTTE, VC .
IEEE TRANSACTIONS ON PARTS HYBRIDS AND PACKAGING, 1977, 13 (03) :194-198