High-value MOS capacitor arrays in ultradeep trenches in silicon

被引：32

作者：

Roozeboom, F ^{[1
]}

Elfrink, R ^{[1
]}

Verhoeven, J ^{[1
]}

van den Meerakker, J ^{[1
]}

Holthuysen, F ^{[1
]}

机构：

[1] Philips Res, NL-5656 AA Eindhoven, Netherlands

来源：

MICROELECTRONIC ENGINEERING | 2000年 / 53卷 / 1-4期

关键词：

D O I：

10.1016/S0167-9317(00)00383-X

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fully Si-compatible process has been developed to manufacture 6-inch silicon (100) wafers with patterns of trenches, several hundreds of mu m deep with a width and pitch of a few mu m. The hundredfold enlarged silicon surface is used as a substrate for MOS (Metal-Oxide-Semiconductor) capacitor arrays with a capacitance of 1 nF to 1 mu F. The specific capacitance was as high as 100 nF/mm(2).

引用

页码：581 / 584

页数：4

共 8 条

[1] ANISOTROPIC ETCHING OF SILICON [J].