A lock-based cache coherence protocol for scope consistency

被引:14
作者
Weiwu Hu
Weisong Shi
Zhimin Tang
Ming Li
机构
[1] Chinese Academy of Sciences,Institute of Computing Technology
关键词
Memory consistency; cache coherence; lock-based protocol; directory-based protocol; scope consistency;
D O I
10.1007/BF02946599
中图分类号
学科分类号
摘要
Directory protocols are widely adopted to maintain cache coherence of distributed shared memory multiprocessors. Although scalable to a certain extent, directory protocols are complex enough to prevent it from being used in very large scale multiprocessors with tens of thousands of nodes. This paper proposes a lock-based cache coherence protocol for scope consistency. It does not rely on directory information to maintain cache coherence. Instead, cache coherence is maintained through requiring the releasing processor of a lock to store all write-notices generated in the associated critical section to the lock and the acquiring processor invalidates or updates its locally cached data copies according to the write notices of the lock. To evaluate the performance of the lock-based cache coherence protocol, a software DSM system named JIAJIA is built on network of workstations. Besides the lock-based cache coherence protocol, JIAJIA also characterizes itself with its shared memory organization scheme which combines the physical memories of multiple workstations to form a large shared space. Performance measurements with SPLASH2 program suite and NAS benchmarks indicate that, compared to recent SVM systems such as CVM, higher speedup is achieved by JIAJIA. Besides, JIAJIA can solve large scale problems that cannot be solved by other SVM systems due to memory size limitation.
引用
收藏
页码:97 / 109
页数:12
相关论文
共 7 条
[1]  
Lamport L(1979)How to make a multiprocessors computer that correctly executes multiprocessor programs IEEE Transactions on Computers 28 690-691
[2]  
Hu W(1998)A framework of memory consistency models Journal of Computer Science and Technology 13 110-124
[3]  
Shi W(1992)SPLASH: Stanford parallel applications for shared memory Computer Architecture News 20 5-44
[4]  
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