A DDS Synthesizer with Digital Time Domain Interpolator

被引:8
作者
Timo Rahkonen
Harri Eksyma
Antti Mäntyniemi
Heikki Repo
机构
[1] University of Oulu,Electronics Laboratory, Dept. of Electrical Engineering and Infotech, Oulu
[2] Martis Tellabs,undefined
来源
Analog Integrated Circuits and Signal Processing | 2001年 / 27卷
关键词
direct digital synthesis; time-to-digital converter; spectral purity;
D O I
暂无
中图分类号
学科分类号
摘要
A DDS type circuit structure for producing numericallyprogrammable square wave clock signal is presented. The high speed D/Aconverter needed in conventional DDS systems is replaced by an\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document} $$N$$ \end{document} tap delay line time domain interpolator thateffectively increases the sampling rate by a factor of\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document} $$N$$ \end{document}. Thus the circuit can be used up to full clock rate withoutimage filtering. A prototype IC with clock frequency of 30 MHz, 5 bitinterpolator and SFDR of −40 dBc up to 10 MHz and −33 dBcup to 15 MHz has been designed and tested.
引用
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页码:109 / 116
页数:7
相关论文
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Nakagawa T.(undefined)An integrated digital CMOS time-to-digital converter with sub-gatedelay resolution undefined undefined undefined-undefined
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Rahkonen T.(undefined)undefined undefined undefined undefined-undefined
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