An Effective Multi-Chip BIST Scheme

被引:2
作者
Yervant Zorian
Hakim Bederr
机构
[1] LogicVision,
[2] Texas Instruments,undefined
来源
Journal of Electronic Testing | 1997年 / 10卷
关键词
MCM testing; built-in self-test; DFT;
D O I
暂无
中图分类号
学科分类号
摘要
This paper addresses the general problem of module level test ofassembled Multi-Chip Modules (MCMs) and specifically the performancetest of such modules. It presents a novel solution based-on built-in self-test (BIST). This solutionaugments the conventional single-chip BIST approach, which is used to produce individual good dies, to an effective multi-chip BIST solution. The multi-chip BIST puts the entire module in a self-test mode. The self-test mode not only provides effective detection of static and dynamic faults, but also identifies the failed elements, i.e., bad dies or substrate. The multi-chip self-test scheme is based on pseudo-random test generation and uses multi-signature evaluation. The hardware design ofmulti-chip and single-chip self-test blocks is combined under one common architecture called the Dual BIST Architecture. The paper introduces the Dual BIST Architecture and demonstrates a set of design configurations to implement it. The presented BIST solution provides a reliable static and dynamic test at the module as well as the bare die levels.
引用
收藏
页码:87 / 95
页数:8
相关论文
共 3 条
[1]  
Zorian Y.(1994)A Structured Testability Approach for Multi-Chip Modules Based on BIST and Boundary-Scan IEEE Trans. on Components, Packaging, and Manufacturing technology: Advanced Packaging 17 283-290
[2]  
Zorian Y.(1992)An Effective BIST Scheme for ROMs IEEE Trans. on Computers 41 646-653
[3]  
Ivanov A.(undefined)undefined undefined undefined undefined-undefined