The discovery and removal of logic design errors early in the development cycle is critical to timely availability of market-driven processor products. This paper describes the part played by simulation in the verification of the high-end models of the IBM Enterprise System/9000(TM) (ES/9000(TM)) processor family, and how that effort advanced the state of the art of logic design simulation. The increased complexity of the ES/9000 design over that of the IBM Enterprise System/3090(TM) (ES/3090(TM)) necessitated a larger simulation effort. New tools and methods were developed. Two simulation missions were established. Element simulation addressed ES/9000 functional elements (e.g., the storage controller) individually using the Compiled Enhanced Functional Simulator (CEFS), a software tool. System simulation tested two or more functional elements together using the Engineering Verification Engine (EVE), a special-purpose hardware parallel processor, and an attached IBM 3092 Processor Controller (PCE). The results achieved by simulation are discussed, together with the methods used and the impact these results had on the overall verification of the ES/9000 Models 820 and 900.