DESIGN CONSIDERATIONS FOR DC SQUIDS FABRICATED IN DEEP SUBMICRON TECHNOLOGY

Design rules for scaling dc SQUID junctions to optimize SQUID performance have been well known for over a decade, and verified down to the sub-micron regime. Practical SQUIDs having well coupled input coils of useable inductance have generally been fabricated at the 2 - 5-mu-m level of lithography. Other technologies, silicon in particular, are now routinely practiced at the 0.5-mu-m level of lithography with impressive demonstrations at the 0.1 -0.25-mu-m level not uncommon. In this paper the implications of applying such fabrication capability to advance dc SQUID technology are explored. In particular the issues of scaling practical dc SQUIDs down to the 0.1 - 0.25-mu-m regime are examined, using as a prototype design the basic washer SQUID with a spiral input coil 1. A technical path is mapped out that leads to a practical SQUID less than 0.05 mm 2 in area with a tightly coupled 2-mu-H input coil, user friendly voltage - flux characteristics, minimal flux creep related hysteresis, and coupled energy sensitivity approaching the quantum limit at 4.2 K.