A MOTION ESTIMATOR FOR LOW BIT-RATE VIDEO CODEC

被引：7

作者：

JEHNG, YS

CHEN, LG

CHIUEH, TD

机构：

[1] Department of Electrical Enaineerina National Taiwan University, Taipei

来源：

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS | 1992年 / 38卷 / 02期

关键词：

D O I：

10.1109/30.142860

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new component performing motion estimation is presented. This chip is designed based on the three step hierarchical search block-matching algorithm and can be applied to image communication on ISDN (H.261 standard), MPEG, TV transmission, HDTV, etc. The practical architectural design techniques and the chip features are discussed.

引用

页码：60 / 69

页数：10

共 7 条

[1]

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Bheda, Hemant ;

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[3] ARRAY ARCHITECTURES FOR BLOCK MATCHING ALGORITHMS [J].

KOMAREK, T ;

PIRSCH, P .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1989, 36 (10) :1301-1308

[4]

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[5] MOTION ESTIMATION VLSI ARCHITECTURE FOR IMAGE-CODING [J].

PRIVAT, G ;

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PROCEEDINGS - IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN : VLSI IN COMPUTERS & PROCESSORS, 1989, :78-81

[6]

VOS LD, 1989, IEEE T CIRCUITS SYST, V36, P1309, DOI DOI 10.1109/31.44347

[7] A FAMILY OF VLSI DESIGNS FOR THE MOTION COMPENSATION BLOCK-MATCHING ALGORITHM [J].

YANG, KM ;

SUN, MT ;

WU, L .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1989, 36 (10) :1317-1325

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