A 40-NS 64-MB DRAM WITH 64-B PARALLEL DATA BUS ARCHITECTURE

This paper describes circuit techniques for wide I/O data path and high-speed 64-Mb DRAM. A hierarchical data bus structure using double-level metallization has been developed to form 64-b parallel data bus lines without increasing the chip size. A current-sensing data bus amplifier, developed to sense the 64-b data bus signal in parallel, has made the wide I/O data path structure possible. A direct-sensing-type column gate circuit with the READ/WRITE separated select line scheme achieves 40-ns RAS access. A shielded bit-line three-dimensional stacked-capacitor cell with a double-fin storage capacitor stores sufficient charge while the bit-line capacitance shows a reasonable value for sensing the data.