A STACKED-CMOS CELL TECHNOLOGY FOR HIGH-DENSITY SRAMS

被引：6

作者：

UEMOTO, Y

FUJII, E

NAKAMURA, A

SENDA, K

TAKAGI, H

机构：

[1] Electronics Research Laboratory, Matsushita Electronics Corporation, Osaka, 569, Saiwai-cho, 1–1, Takatsuki

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1992年 / 39卷 / 10期

关键词：

Semiconductor storage;

D O I：

10.1109/16.158809

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The stacked-CMOS SRAM cell technology for high-density SRAM's has been developed. It has been found that the increase of the on-current of the TFT load leads not only to the increase of the cell noise margin, but also to the reduction of the cell area. The improvement of the electrical characteristics of the TFT load has been achieved by enlarging the grains of the polysilicon film through the use of a novel solid phase growth technique. As a result, TFT loads with on/off current ratio of 10(5) and off-current of 0.07 pA/mu-m have been obtained, both promising for high-density SRAM's.

引用

页码：2359 / 2363

页数：5

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