VLSI IMPLEMENTATION OF AN EFFICIENT ASIC ARCHITECTURE FOR REAL-TIME ROTATION OF DIGITAL IMAGES

This paper describes the design and the VLSI implementation of a novel architecture that performs image rotation in real time. In order to improve throughput, we divide an image-frame into a number of windows. The rotation of each window-center as well as the final displacement of individual pixels within a window is then calculated. A CORDIC-based scheme is used to compute the displacement of a pixel. Our architectural design is incorporated into a chip that has been laid out using VTI (VLSI Technology Inc.) tools obeying the 1.5 mu m SCMOS design rules. The chip owes its high processing capability to a combination of pipelining and parallel-processing techniques. For a clock frequency greater than 10.6 MHz, we can perform the rotation of a 512 x 512 gray-level digital image at the rate of 30 frames per second. The chip utilizes around 35,000 transistors and has an estimated silicon area of 211 mils x 276 mils.