THE OLYMPUS SYNTHESIS SYSTEM

被引：22

作者：

DEMICHELI, G ^{[1
]}

KU, D ^{[1
]}

MAILHOT, F ^{[1
]}

TRUONG, T ^{[1
]}

机构：

[1] IBM CORP,ALMADEN RES CTR,SAN JOSE,CA

来源：

IEEE DESIGN & TEST OF COMPUTERS | 1990年 / 7卷 / 05期

基金：

美国国家科学基金会;

关键词：

D O I：

10.1109/54.60605

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Olympus, a synthesis system for digital design developed at Stanford University, is a vertically integrated set of tools for multilevel synthesis, technology mapping, and simulation. The system supports the synthesis of ASICs from behavioral descriptions written in a hardware description language called HardwareC. Two internal models represent the hardware at different levels of abstraction and provide a way to pass design information among different tools. Olympus has been used to design three ASIC chips at Stanford, and it has been tested against benchmark circuits for high-level and logic synthesis. © 1990 IEEE

引用

页码：37 / 53

页数：17

共 13 条

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[4]

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[5]

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[6]

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[7]

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[9]

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[10]

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