A HIGH-SPEED 64K CMOS RAM WITH BIPOLAR SENSE AMPLIFIERS

A TTL-compatible 64K static RAM with new CMOS-bipolar circuitry has been developed, using a 1. 2 mu m MoSi gate n-well CMOS-bipolar technology. Address access time is typically 28 ns, with 225 mw active power and 100 nw standby power. A CMOS six transistor memory cell is used. The cell size is 18 multiplied by 20 mu m, and the chip size is 5. 95 multiplied by 6. 84 mm. The n-p-n transistors are used in the sense amplifiers, voltage regulators, and level clamping circuits. The bipolar sense amplifiers reduce the detectable bit line swing thus improving the worst-case bit line delay time and the sensing delay time. In order to reduce the large distributed RC delay, such as the word line delay, the MoSi layer was used for the gate materials. The n-well CMOS process described here is based on a scaled CMOS process, and collector-isolated n-p-n transistors and CMOS are integrated simultaneously without adding any extra process steps and without causing any degradation of CMOS characteristics.