TRENDS IN MEGABIT DRAM CIRCUIT-DESIGN

The state of the art in megabit dynamic random access memory (DRAM) circuit and chip design is reviewed in terms of essential design parameters such as signal-to-noise ratio, power dissipation, and speed. The key results obtained are 1) the memory cell signal charge has decreased gradually with an increase in memory cell size, despite the vertically structured cell designs. To offset this decrease, multi-divided data- (bit) line structures, low-power design, and transposition of folded data lines are essential. 2) To reduce power dissipation, an increase in the maximum refresh cycle and multi-divided data lines combined with shared I/O in addition to a reduced operating voltage are efficient. 3) A BiCMOS circuit provides a high-speed access time with low cost due to the high drivability of the driver and the high sensitivity of the amplifier. Based on this discussion, it is predicted that the current DRAM technology might be diversified coexistently to a large-memory-capacity oriented technology and to a high-speed oriented one, posing power-supply standardization as a continuing serious concern. © 1990 IEEE