A VIDEO DSP WITH A MACROBLOCK-LEVEL-PIPELINE AND A SIMD TYPE VECTOR-PIPELINE ARCHITECTURE FOR MPEG2 CODEC

被引：5

作者：

TOYOKURA, M

KODAMA, H

MIYAGOSHI, E

OKAMOTO, K

GION, M

MINEMARU, T

OHTANI, A

ARAKI, T

TAKENO, H

AKIYAMA, T

WILSON, B

AONO, K

机构：

[1] MATSUSHITA ELECT IND CO LTD,DIV CORP PROD DEV,AUDIO VIDEO INFORMAT TECHNOL LAB,KADOMA,OSAKA 571,JAPAN

[2] ASIA MATSUSHITA ELECT PTE LTD,AV INFORMAT RES CTR,SINGAPORE 1953,SINGAPORE

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1994年 / 29卷 / 12期

关键词：

D O I：

10.1109/4.340420

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A video DSP with macroblock-level-pipeline and a SIMD type vector-pipeline architecture (VDSP2) has been developed, using 0.5 mu m triple-layer-metal CMOS technology. This 17.00 mm x 15.00 mm chip consists of 2.5 M transistors, and operates at 100 MHz. The real-time encoder and decoder specified in the MPEG2 main profile at the main level can be realized with two VDSP2's and a motion estimation (ME) unit, and one VDSP2, respectively, at an 80 MHz clock rate, with a total power dissipation of 4.2 W at 3.3 V.

引用

页码：1474 / 1481

页数：8

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