DIBL IN SHORT-CHANNEL NMOS DEVICES AT 77-K

Detailed experimental and two-dimensional numerical simulation results on drain-induced barrier lowering (DIBL) versus channel length at 300 and 77 K in short-channel NMOS devices are presented. It is found that by decreasing the temperature from 300 to 77 K, DIBL in NMOS devices with effective channel lengths (L) from 0.5 to 2.0-mu-m shows the following unique and interesting feature: it is improved for the range of L < 0.6-mu-m and L > 1.2-mu-m, but is worse for L between 0.6 and 1.2-mu-m. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, that includes device modeling at cryogenic temperatures, was used to investigate this unique characteristic. The simulations shows that lowering the temperature from 300 to 77 K has the following two effects: a) a shorter lateral depletion width between the source or drain and the channel, but a wider vertical depletion width between the source or drain and the substrate; and b) the channel current would be pushed back towards the surface. Therefore, the measured DIBL characteristics could be explained physically as the transition from surface DIBL through the subsurface DIBL to the bulk DIBL or punchthrough effect at 300 K, but almost a surface DIBL for the whole range of channel length variation at 77 K. Design considerations of the channel doping profile in short-channel NMOS device for low-temperature operation based on keeping the same DIBL and V(TH) as required for room-temperature operation are also briefly discussed.