COOPERATIVE SHARED-MEMORY - SOFTWARE AND HARDWARE FOR SCALABLE MULTIPROCESSORS

We believe the paucity of massively parallel, shared-memory machines follows from the lack of a shared-memory programming performance model that can inform programmers of the cost of operations (so they can avoid expensive ones) and can tell hardware designers which cases are common (so they can build simple hardware to optimize them). Cooperative shared memory, our approach to shared-memory design, addresses this problem. Our initial implementation of cooperative shared memory uses a simple programming model, called Check-ln/Check-Out (CICO), in conjunction with even simpler hardware, called Dir(1)SW. In CICO, programs bracket uses of shared data with a check_out directive marking the expected first use and a check_in directive terminating the expected use of the data. A cooperative prefetch directive helps hide communication latency. Dir(1)SW is a minimal directory protocol that adds little complexity to message-passing hardware, but efficiently supports programs written within the CICO model.