A 50-NS 16-MB DRAM WITH A 10-NS DATA RATE AND ON-CHIP ECC

A high-speed 16-Mb DRAM chip with on-chip error-correcting code (ECC), which supports either 11/11 or 12/10 RAS/CAS addressing and operates on a 3.3- or 5-V power supply, is described. It can be packaged as a 2-Mb X 8, 4-Mb X 4, 8-Mb X 2, or 16-Mb X 1 DRAM, and is capable of operating in fast page mode, static column mode, or toggle mode. Speed and flexibility are achieved by a pipeline layout and on-chip SRAM’s that buffer entire ECC words. The use of redundant word and bit lines in conjunction with the ECC produces a synergistic fault-tolerance effect. © 1990 IEEE