IMAGE-PROCESSING REGULARIZATION FILTERS ON LAYERED ARCHITECTURE

被引:22
作者
KOBAYASHI, H
MATSUMOTO, T
YAGI, T
SHIMMI, T
机构
[1] WASEDA UNIV,DEPT ELECT ENGN,3-4-1 OHKUBO,SHINJUKU KU,TOKYO 169,JAPAN
[2] YOKOGAWA ELECT CORP,MUSASHINO,JAPAN
[3] KYUSHU INST TECHNOL,KITAKYUSHU 804,JAPAN
关键词
REGULARIZATION; VISION CHIP; LAYERED ARCHITECTURE; ANALOG CMOS; IMAGE PROCESSING; SMART SENSOR;
D O I
10.1016/0893-6080(93)90002-E
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Layered architecture is proposed for solving a class of regularization problems in image processing. There are two major hurdles in the implementation of regularization filters with second or higher order smoothness constraints: (a) Stability: With second or higher order constraints, a direct implementation of a regularization filter necessitates negative conductance which, in turn, gives rise to stability problems. (b) Wiring Complexity: A direct implementation of an N-th order regularization filler requires wiring between every pair of k-th nearest nodes for all k, 1 less-than-or-equal-to k less-than-or-equal-to N. Even though one of the authors managed to layout an N = 2 chip, the implementation of an N greater-than-or-equal-to 3 chip would be an extremely difficult, if not impossible, task. The regularization filter architecture proposed here (a) requires no negative conductance,- and (b) necessitates wiring only between nearest nodes. Smoothing-Contrast-Enhancement filter is given as an example of application. Since this filter is extremely fast, it will have a natural application to smart sensing, i. e., to the simultaneous achievement of sensing and processing. It is also explained how this architecture has been inspired by physiological findings on lower vertebrate retina by one of the authors.
引用
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页码:327 / 350
页数:24
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