DESIGN AND IMPLEMENTATION OF A 3D-LSI IMAGE SENSING PROCESSOR

被引:10
作者
KIOI, K
SHINOZAKI, T
TOYOYAMA, S
SHIRAKAWA, K
OHTAKE, K
TSUCHIMOTO, S
机构
[1] Central Research Laboratories, Sharp Corporation, Tenri, Nara, 632, 2613–1, Ichinomoto
关键词
D O I
10.1109/4.148321
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A four-story structured image sensing processor has been implemented, with three-dimensional LSI (3D-LSI) technology, integrating 5040 pixel photodiodes and 0.22 million transistors on a 14.3-mm square single die. The implemented chip allows a large degree of data parallelism in image computations where the image sensor unit operates without synchronous clocks. The chip, which is a second prototype, is able to sense 12 characters at the same time, and can recognize 64 different characters in upper and lower case, Arabic numerals, and some symbols, each consisting of a 10 x 14 matrix. The chip is made of a large number of simple processing elements working in parallel, which speeds up computation. The time needed to identify a sensed image as a memorized character is about 3-mu-s. Successful measurements of the principal functions verify the usefulness of the chip.
引用
收藏
页码:1130 / 1140
页数:11
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