THE CMOS GATE FOREST - AN EFFICIENT AND FLEXIBLE HIGH-PERFORMANCE ASIC DESIGN ENVIRONMENT

The basic concepts of the second-generation gate arrays are described. The most important architectures that were used to implement the different concepts are discussed. An overview of the current status of a number of typical sea-of-gates masters is given. A number of quality marks have been defined along which the different architectures can be evaluated. These quality marks range from microarchitecture aspects such as isolation techniques and connectability of the core cells, to macro aspects such as distribution functions. Using these quality marks for reference, the Gate Forest is discussed. The Gate Forest is seen as a major extension of the sea-of-gates principle. It differs from the extant sea-of-gates concept in several important aspects. It is based on a hierarchical concept, both in architecture and design. It combines flexibility and efficiency in one environment by providing transistor-level optimization together with cell library support for different logic design styles. It furthermore supports the efficient implementation of different types of memory in any desired location. The current status of the second generation of the Gate Forest is also briefly described.