AN OFFSET REDUCTION TECHNIQUE FOR USE WITH CMOS INTEGRATED COMPARATORS AND AMPLIFIERS

被引：26

作者：

ATHERTON, JH

SIMMONDS, HT

机构：

[1] Siemens Corporate Research Inc., Princeton

[2] Applied Optronics Corporation, South Plainfield, NJ

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1992年 / 27卷 / 08期

关键词：

D O I：

10.1109/4.148325

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Popular methods for reducing the input offset voltage of comparators and amplifiers are reviewed. A comparator that adjusts its own offset either at power-up or in response to a control input is presented. The nature of the offset adjustment is such that the comparator is capable of continuous-time operation. Room-temperature offsets in the range of -100 to +100-mu-V are achievable. Adjusted offsets exhibit a temperature coefficient on the order of -1-mu-V/degrees-C.

引用

页码：1168 / 1175

页数：8