A SINGLE POLY-EEPROM CELL STRUCTURE FOR USE IN STANDARD CMOS PROCESSES

A single poly EEPROM cell structure implemented in a standard CMOS Process is developed. It consists of adjacently placed NMOS and PMOS transistors with an electrically isolated common polysilicon gate. The common gate works as a ''floating gate.'' The inversion layer as ''control node (gate).'' Test chips which were fabricated in a 0.8 mum/150 angstrom standard CMOS logic process showed 5-9 V of threshold voltage shift and more than 10000 cycles of endurance with good data retention under high temperature. This EEPROM cell can be easily integrated with CMOS digital and analog circuits.