INTERCONNECT PERFORMANCE LIMITS ON GIGASCALE INTEGRATION (CSI)

被引:4
作者
MEINDL, JD
DAVIS, J
机构
[1] Microelectronics Research Center, Georgia Institute of Technology, Atlanta
关键词
GIGASCALE INTEGRATION; INTERCONNECT PERFORMANCE;
D O I
10.1016/0254-0584(95)01509-4
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Future opportunities for gigascale integration (GSI) will be governed by a hierarchy of limits whose levels can be codified as: (i) fundamental, (ii) material, (iii) device, (iv) circuit and (v) system. Performance limits on interconnects at all levels of this hierarchy are elucidated by plotting the square of reciprocal length of the interconnect versus the response time of the interconnect circuit. Fundamental and material limits are defined essentially by the time of flight of a lossless transmission line. The response time of a canonical distributed resistance-capacitance network imposes the principal device limit, while the dominant circuit limit is imposed by the response time of a driver-interconnect-load circuit. System limits are determined by the response time required from the longest global interconnect and hence chip size.
引用
收藏
页码:161 / 166
页数:6
相关论文
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