The internal behavior of a typical n-p-n** minus -n** plus high voltage power transistor is presented for several specific steady-state operating conditions obtained from a two-dimensional mathematical model. Internal self-heating and avalanche multiplication effects are taken into account. Poisson's equation, electron and hole continuity equations, and the heat flow equation are solved numerically in a two-dimensional region with the input parameters of device dimensions, doping profile, boundary conditions for external contacts, and various material constants for silicon. The collector n** minus -n** plus interface is the region of high electrical and thermal stress that causes second breakdown failure at high-voltage and high-current operating conditions. The combined effects of various high-injection levels are illustrated.