BANDWIDTH OPTIMIZATION OF A LOW-POWER, HIGH-SPEED CMOS CURRENT OP AMP

A current op amp with a differential output and a single-ended input can be configured from a single second generation current conveyor and an output stage with a differential floating current source. Owing to a very simple basic configuration with a single dominant pole, this design combines a high bandwidth with a high open loop gain. In this paper we present the basic configuration, derive the fundamental equations for the performance of the op amp, and describe some design considerations with respect to an optimization of the op amp for a high bandwidth. Simulation results are given from a commercially available 2 mu m CMOS process resulting in an open loop differential gain of 94dB and a gain-bandwidth product of 128MHz at a supply voltage of 3V and a supply current of 25 mu A. The design has been experimentally verified through a test circuit and experimental results from this confirm the expected behaviour.