DIRECTORY-BASED CACHE COHERENCE IN LARGE-SCALE MULTIPROCESSORS

被引：57

作者：

CHAIKEN, D

FIELDS, C

KURIHARA, K

AGARWAL, A

机构：

[1] MIT,DEPT ELECT ENGN & COMP SCI,CAMBRIDGE,MA 02139

[2] MIT,ATHENA PROJECT,CAMBRIDGE,MA 02139

来源：

COMPUTER | 1990年 / 23卷 / 06期

关键词：

D O I：

10.1109/2.55500

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

[No abstract available]

引用

页码：49 / 58

页数：10

共 12 条

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[2] CACHE COHERENCE PROTOCOLS - EVALUATION USING A MULTIPROCESSOR SIMULATION-MODEL [J].

ARCHIBALD, J ;

BAER, JL .

ACM TRANSACTIONS ON COMPUTER SYSTEMS, 1986, 4 (04) :273-298

[3]

CENSIER LM, 1978, IEEE T COMPUT, V27, P1112

[4]

EGGERS SJ, 1989, 3RD P INT C ARCH SUP, P257

[5]

Goodman J. R., 1983, 10th Annual International Conference on Computer Architecture Conference Proceedings, P124, DOI 10.1145/800046.801647

[6] DISTRIBUTED-DIRECTORY SCHEME - SCALABLE COHERENT INTERFACE [J].

JAMES, DV ;

LAUNDRIE, AT ;

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SOHI, GS .

COMPUTER, 1990, 23 (06) :74-77

[7]

KRANZ D, 1989, JUN ACM SIGPLAN 89 C, P81

[8]

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[9]

LAMPORT L, 1979, IEEE T COMPUT, V28, P690, DOI 10.1109/TC.1979.1675439

[10]

PATEL JH, 1982, IEEE T COMPUT, V31, P296, DOI 10.1109/TC.1982.1675995

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