COMPARISON OF FLOATING GATE NEURAL NETWORK MEMORY CELLS IN STANDARD VLSI CMOS TECHNOLOGY

Several floating gate MOSFET structures, for potential use as analog memory elements in neural networks, have been fabricated in a standard 2-mu-m double-polysilicon CMOS process. Their physical and programming characteristics are compared with each other and with similar structures reported in the literature. None of the circuits under consideration require special fabrication techniques. The criteria used to determine the structure most suitable for neural network memory applications include the symmetry of charging and discharging characteristics, programming voltage magnitudes, the area required, and the effectiveness of geometric field enhancement techniques. This work provides a layout for an analog neural network memory based on previously unexplored criteria and results. We have found that the best designs a) use the poly1 to poly2 oxide for injection; b) need not utilize "field enhancement" techniques; c) use poly1 to diffusion oxide for a coupling capacitor; and d) size capacitor ratios to provide a wide range of possible programming voltages.