A MONOLITHIC 2.3-GB/S 100-MW CLOCK AND DATA RECOVERY CIRCUIT IN SILICON BIPOLAR TECHNOLOGY

A monolithic clock and data recovery PLL circuit is implemented in a digital silicon bipolar technology without modification. The only external component used is the loop filter capacitor. A self-aligned data recovery architecture combined with a novel phase-detector design eliminates the need for non-linear processing and phase shifter stages. This enables a simpler design with low power and reduced dependence on the bit rate. At 2.3 Gb/s, the test chip consumes 100 mW from a supply, excluding the input and output buffers. The worst-case rms jitter of the recovered clock is less than 14 ps with 2(23) - 1 pseudorandom bit sequence.