LOGIC DESIGN VERIFICATION VIA TEST-GENERATION

[1] Breuer M. A., 1976, DIAGNOSIS RELIABLE D

[2] BRYANT RE, 1985, MAY CHAP HILL C VLSI

[3] CHANDRASHEKHAR M, 1987, P DES AUT C, P277

[4] CHANG CL, 1974, SYMBOLIC LOGIC MECHA

[5] DARRINGER JA, 1979, JUN P DES AUT C, P375

[6] DONATH WE, 1976, IBM TECH DISCLOSURE, V18

[7] HUGHES JLA, 1984, P INT TEST C ITC, P52

[8] JOHANSSEN D, 1979, P DESIGN AUTOMAT C

[9] MARUYAMA F, 1985, COMPUTER FEB, P22

[10] ODAWARA G, 1986, P DESIGN AUTOMAT C

[1] Breuer M. A., 1976, DIAGNOSIS RELIABLE D

[2] BRYANT RE, 1985, MAY CHAP HILL C VLSI

[3] CHANDRASHEKHAR M, 1987, P DES AUT C, P277

[4] CHANG CL, 1974, SYMBOLIC LOGIC MECHA

[5] DARRINGER JA, 1979, JUN P DES AUT C, P375

[6] DONATH WE, 1976, IBM TECH DISCLOSURE, V18

[7] HUGHES JLA, 1984, P INT TEST C ITC, P52

[8] JOHANSSEN D, 1979, P DESIGN AUTOMAT C

[9] MARUYAMA F, 1985, COMPUTER FEB, P22

[10] ODAWARA G, 1986, P DESIGN AUTOMAT C