A 66 MHZ, 32-CHANNEL ANALOG MEMORY CIRCUIT WITH DATA SELECTION FOR FAST SILICON DETECTORS

An analog memory array with 64 memory cells for each channel has been designed and manufactured in CMOS. A new skip logic controller allows to write at 66 MHz without dead time and to read out at a lower frequency simultaneously. The input circuit is charge-sensitive and integrates continuously. Pedestal nonuniformity is 1.4 mV rms from cell-to-cell and 3.5 mV rms between channels. The linearity range is - 2.5 to + 1.5 V, which corresponds to 11 bits. The chip has been used in a particle detection test.