FULLY SYMMETRIC COOLED CMOS ON (110) PLANE

被引:8
作者
AOKI, M
YANO, K
MASUHARA, T
SHIMOHIGASHI, K
机构
关键词
D O I
10.1109/16.30955
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:1429 / 1433
页数:5
相关论文
共 12 条
[1]   OPTIMUM CRYSTALLOGRAPHIC ORIENTATION OF SUBMICROMETER CMOS DEVICES OPERATED AT LOW-TEMPERATURES [J].
AOKI, M ;
YANO, K ;
MASUHARA, T ;
IKEDA, S ;
MEGURO, S .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1987, 34 (01) :52-57
[2]   PERFORMANCE AND HOT-CARRIER EFFECTS OF SMALL CRYO-CMOS DEVICES [J].
AOKI, M ;
HANAMURA, S ;
MASUHARA, T ;
YANO, K .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1987, 34 (01) :8-18
[3]  
AOKI M, 1983, NAT C REC SEMICONDUC, P82
[4]  
AOKI M, 1987, S VLSI, P49
[5]   VERY SMALL MOSFETS FOR LOW-TEMPERATURE OPERATION [J].
GAENSSLEN, FH ;
RIDEOUT, VL ;
WALKER, EJ ;
WALKER, JJ .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1977, 24 (03) :218-229
[6]   TEMPERATURE-DEPENDENT THRESHOLD BEHAVIOR OF DEPLETION MODE MOSFETS [J].
GAENSSLEN, FH ;
JAEGER, RC .
SOLID-STATE ELECTRONICS, 1979, 22 (04) :423-430
[7]   LOW-TEMPERATURE CMOS 8X8 BIT MULTIPLIERS WITH SUB-10-NS SPEEDS [J].
HANAMURA, S ;
AOKI, M ;
MASUHARA, T ;
MINATO, O ;
SAKAI, Y ;
HAYASHIDA, T .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1987, 34 (01) :94-100
[8]  
HANAMURA S, 1983, S VLSI, P210
[9]   DESIGN AND EXPERIMENTAL TECHNOLOGY FOR 0.1-MU-M GATE-LENGTH LOW-TEMPERATURE OPERATION FETS [J].
SAIHALASZ, GA ;
WORDEMAN, MR ;
KERN, DP ;
GANIN, E ;
RISHTON, S ;
ZICHERMAN, DS ;
SCHMID, H ;
POLCARI, MR ;
NG, HY ;
RESTLE, PJ ;
CHANG, THP ;
DENNARD, RH .
IEEE ELECTRON DEVICE LETTERS, 1987, 8 (10) :463-466
[10]   EFFECTS OF CRYSTALLOGRAPHIC ORIENTATION ON MOBILITY SURFACE STATE DENSITY AND NOISE IN P-TYPE INVERSION LAYERS ON OXIDIZED SILICON SURFACES [J].
SATO, T ;
TAKEISHI, Y ;
HARA, H .
JAPANESE JOURNAL OF APPLIED PHYSICS, 1969, 8 (05) :588-+