USE OF SCREENING AND RESPONSE-SURFACE EXPERIMENTAL-DESIGNS FOR DEVELOPMENT OF A 0.5-MU-M CMOS SELF-ALIGNED TITANIUM SILICIDE PROCESS

被引：10

作者：

JONES, RE

MELE, TC

机构：

[1] Advanced Products Research and Development Laboratory, Motorola, Inc., Austin, TX

来源：

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING | 1991年 / 4卷 / 04期

关键词：

D O I：

10.1109/66.97810

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

A manufacturable self-aligned titanium silicide process for 0.5-mu-m CMOS technologies has been developed. Factorial and fractional-factorial screening experiments, as well as physical models, were used to identify important process factors. Central-composite and D-optimal response surface designs were employed to optimize the process; short-loop process and device experiments and 0.5-mu-m technology static random access memory (SRAM) circuit flows were used. By employing this comprehensive experimental design methodology, problems with diode leakage and silicide-to-silicon contact resistance were resolved, and specified device characteristics were achieved.

引用

页码：281 / 287

页数：7

共 15 条

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