A SELECTIVE SIO2 FILM-FORMATION TECHNOLOGY USING LIQUID-PHASE DEPOSITION FOR FULLY PLANARIZED MULTILEVEL INTERCONNECTIONS

被引:63
作者
HOMMA, T
KATOH, T
YAMADA, Y
MURAO, Y
机构
[1] ULSI Device Development Laboratories, NEC Corporation, Sagamihara
关键词
Integrated circuit manufacture;
D O I
10.1149/1.2220834
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
A selective SiO2 film-formation technology using liquid-phase deposition (LPD) around room temperature for fully planarized multilevel interconnections is developed. The LPD technique utilizes supersaturated hydrofluosilicic acid (H2SiF6) aqueous solution as a source liquid. The LPD-SiO2 films can be selectively formed on chemical vapor deposition (CVD) SiO2 underlayers in the trenches between photoresist patterns or tungsten wiring with photoresist as mask. For polysilicon patterns with photoresist masks, the LPD-SiO2 films creep along the polysilicon and photoresist sidewalls. The selective deposition mechanism can be explained as siloxane oligomers, which are formed in the supersaturated H2SiF6 aqueous solution, have different chemical reactivity between the photoresist and substrate surface. Global planarization of trenches between tungsten wiring is achieved using the selective LPD-SiO2 deposition technique. A fully planarized double-level tungsten interconnection is realized using both selective LPD-SiO2 film deposition and selective tungsten CVD via filling. Low contact resistance of ca. 0.3 OMEGA/unit is achieved for via holes 0.8 mum in diam.
引用
收藏
页码:2410 / 2414
页数:5
相关论文
共 15 条
[1]  
CHIANG C, 1990, IEEE VLSI MULT INT C, P381
[2]  
Coda T., 1987, MATER RES SOC S P, V105, P283
[3]  
FRITZSCHE H, 1986, IEEE VLSI MULTILEVEL, P45
[4]  
HAZUKI Y, 1986, IEEE VLSI MULTILEVEL, P121
[5]   FORMATION OF SILICON DIOXIDE FILMS IN ACIDIC SOLUTIONS [J].
HISHINUMA, A ;
GODA, T ;
KITAOKA, M ;
HAYASHI, S ;
KAWAHARA, H .
APPLIED SURFACE SCIENCE, 1991, 48-9 :405-408
[6]  
HOMMA T, 1991, NEC RES DEV, V32, P315
[7]  
HOMMA T, 1988, INT VLSI MULT INT C, P279
[8]  
HOMMA T, 1990, IEEE JSAP S VLSI TEC, V3
[9]  
KAWAHARA H, 1991, SPIE, V1513, P18
[10]  
KITAOKA M, 1991, SPIE INT C THIN FILM, V1519, P109