PERFORMANCE OF JOSEPHSON ARRAY SYSTEMS RELATED TO FABRICATION TECHNIQUES AND DESIGN

被引:15
作者
MULLER, F
KOHLMANN, J
HEBRANK, FX
WEIMANN, T
WOLF, H
NIEMEYER, J
机构
[1] Physikalisch-Technische Bundesanstalt
关键词
D O I
10.1109/77.403199
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Arrays of Nb/AlOx/Nb Josephson tunnel junctions show de characteristics of high quality when the trilayer is deposited direct on polished Si wafers. Underlayers such as rf-sputtered SiO2, can considerably degrade the junction parameters. These results suggest that voltage standard chips should be produced with a cover instead of a groundplane. First results of attenuation measurements on such circuits are presented and discussed. Furthermore, a new and more simple fabrication process without a window-insulating layer and only two photolithographic steps is presented. Arrays of several thousands of junctions showed no problems of any kind with trappped flux.
引用
收藏
页码:2903 / 2906
页数:4
相关论文
共 12 条
[1]   A NEW SELF-ALIGNING PROCESS FOR WHOLE-WAFER TUNNEL JUNCTION FABRICATION [J].
BLAMIRE, MG ;
EVETTS, JE ;
HASKO, DG .
IEEE TRANSACTIONS ON MAGNETICS, 1989, 25 (02) :1123-1126
[2]  
GURVITCH M, 1983, APPL PHYS LETT, V45, P472
[3]  
HAMILTON CA, 1992, COMMUNICATION
[4]  
HEBRANK FX, UNPUB HYBRID INTEGRA
[5]  
KAMINAMI H, 1993, IEEE T APPL SUPERCON, V3, P2182
[6]   TUNNELING MODEL OF SUPERCONDUCTING PROXIMITY EFFECT [J].
MCMILLAN, WL .
PHYSICAL REVIEW, 1968, 175 (02) :537-&
[7]  
PARK SI, 1993, J KOREAN PHYS SOC, V26, P369
[8]  
POPEL R, 1991, IEEE T INSTRUM MEAS, V140, P298
[9]  
SAKAMOTO Y, 1994, PTB-MITT, V104, P151
[10]   JOSEPHSON JUNCTION ARRAY VOLTAGE STANDARD AT THE ETL [J].
SAKAMOTO, Y ;
YOSHIDA, H ;
SAKURABA, T ;
ODAWARA, A ;
MURAYAMA, Y ;
ENDO, T .
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 1991, 40 (02) :312-316