COMMENTS ON SOURCES OF FAILURES AND YIELD IMPROVEMENT FOR VLSI AND RESTRUCTURABLE INTERCONNECTS FOR RVLSI AND WSI - .1. SOURCES OF FAILURES AND YIELD IMPROVEMENT FOR VLSI

被引：3

作者：

HARDEN, JC ^{[1
]}

机构：

[1] TEXAS A&M UNIV,DEPT ELECT ENGN,COLLEGE STN,TX 77803

来源：

PROCEEDINGS OF THE IEEE | 1986年 / 74卷 / 03期

关键词：

INTEGRATED CIRCUITS - Design;

D O I：

10.1109/PROC.1986.13492

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A deficiency in the formulation of the equation presented by Mangir for yield of redundantly designed VLSI chips is shown. An example is used to establish the inadequacy of the term representing the probability of distributing defects to the redundant modules on a chip. Correction of the formulation is then provided, which results in substantially higher yield estimates for chips with increased levels of redundancy. In a reply, the author contends that the comments have stemmed from an incomplete and premature interpretation of his paper's assumptions, results, and yield formulas.

引用

页码：515 / 516

页数：2