AN ANALOG IMPLEMENTATION OF DISCRETE-TIME CELLULAR NEURAL NETWORKS

被引：72

作者：

HARRER, H ^{[1
]}

NOSSEK, JA ^{[1
]}

STELZL, R ^{[1
]}

机构：

[1] SIEMENS AG,MUNICH,GERMANY

来源：

IEEE TRANSACTIONS ON NEURAL NETWORKS | 1992年 / 3卷 / 03期

关键词：

D O I：

10.1109/72.129419

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

An analog circuit structure for the realization of discrete-time cellular neural networks (DTCNN's) is introduced. The computation is done by a balanced clocked circuit based on the idea of conductance multipliers and operational transconductance amplifiers. The circuit is proposed for a one-neighborhood on a hexagonal grid, but can also be modified to larger neighborhoods and/or other grid topologies. A layout was designed for a standard CMOS process, and the corresponding HSPICE simulation results are given. A test chip containing 16 cells was fabricated, and measurements of the transfer characteristics are provided. The functional behavior is demonstrated for a simple example.

引用

页码：466 / 476

页数：11

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