A 60 NS 256KX1 BIT DRAM USING LD3 TECHNOLOGY AND DOUBLE-LEVEL METAL INTERCONNECTION

被引：1

作者：

KERTIS, RA ^{[1
]}

FITZPATRICK, KJ ^{[1
]}

OHRI, KB ^{[1
]}

机构：

[1] DALLAS SEMICOND CORP,DALLAS,TX

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1984年 / 19卷 / 05期

关键词：

LOGIC CIRCUITS - TRANSISTORS - Applications;

D O I：

10.1109/JSSC.1984.1052193

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A high speed 256K multiplied by 1 bit DRAM, using new circuit design techniques and a scaled n-channel process, has been developed. A row access time of 60 ns has been achieved through the use of short-channel devices and two levels of low resistance interconnect. A staggered matrix precharge was implemented to reduce peak supply current and dI/dt during row precharge. Supply current transients are particularly important at the 256K density level due to the fast cycles rates (approaching 10 MHz) and the large matrix capacitance to be precharged.

引用

页码：585 / 590

页数：6