THE RELATIONSHIP BETWEEN GATE BIAS AND HOT-CARRIER-INDUCED INSTABILITIES IN BURIED-CHANNEL AND SURFACE-CHANNEL PMOSFETS

被引：21

作者：

BRASSINGTON, MP ^{[1
]}

RAZOUK, RR ^{[1
]}

机构：

[1] PHILIPS RES LAB,DEVICE PHYS & MODELING GRP,SUNNYVALE,CA 94088

来源：

关键词：

D O I：

10.1109/16.2458

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：320 / 324

页数：5

共 6 条

[1]

HIRUTA Y, 1986, DEC IEDM, P718

[2] DESIGN TRADEOFFS BETWEEN SURFACE AND BURIED-CHANNEL FETS [J].

HU, GJ ;

BRUCE, RH .

KOYANAGI, M ;

LEWIS, AG ;

MARTIN, RA ;

HUANG, TY ;

CHEN, JY .

[4] HOT-ELECTRON AGING IN P-CHANNEL MOSFETS FOR VLSI CMOS [J].

RADOJCIC, R .

TSUCHIYA, T ;

FREY, J .

[6] HOT-CARRIER-INDUCED DEGRADATION IN P-CHANNEL LDD MOSFETS [J].

TZOU, JJ ;

YAO, CC ;

CHEUNG, R ;

CHAN, HWK .