PREDICTIVE WORST CASE STATISTICAL MODELING OF 0.8-MU-M BICMOS BIPOLAR-TRANSISTORS - A METHODOLOGY BASED ON PROCESS AND MIXED DEVICE CIRCUIT LEVEL SIMULATORS

It has been long recognized that statistical modeling of semiconductor devices for integrated circuit design should start from fluctuations in the fabrication process rather than variations in the compact model parameters. In this paper we discuss the use of mixed level physics-based device/circuit simulation software and semiconductor process simulator in the construction of predictive worst case process conditions for bipolar transistors of the AT&T 0.8-mum BICMOS technology currently being manufactured [1]. Process fluctuations are introduced into the process simulator using Latin Hyper-Cube (Monte Carlo) Sampling method. The methodology presented here is different from previous similar studies in that the compact device model parameter extraction step for each sample process is bypassed and active devices in the circuit are described by the physical device simulator rather than a compact model representation. This eliminates deficiencies associated with compact semiconductor device models. Furthermore, inaccuracies and difficulties introduced by compact model parameter extractions (especially for bipolar transistors) are also eliminated. The method is very useful in identifying critical process steps which determine the electrical performance of the devices and circuits. In order to verify the validity of the methodology, numerical simulation results of the bipolar devices and inverter circuits are checked against device I-V data and inverter circuit measurements.