REDUCED INSTRUCTION SET COMPUTERS

被引:130
作者
PATTERSON, DA
机构
关键词
D O I
10.1145/2465.214917
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
引用
收藏
页码:8 / 21
页数:14
相关论文
共 13 条
  • [1] MORE HARDWARE MEANS LESS SOFTWARE
    BERNHARD, R
    [J]. IEEE SPECTRUM, 1981, 18 (12) : 30 - 37
  • [2] Chaitin G. J., 1982, SIGPLAN Notices, V17, P98, DOI 10.1145/872726.806984
  • [3] Fisher J. A., 1983, 10th Annual International Conference on Computer Architecture Conference Proceedings, P140, DOI 10.1145/800046.801649
  • [4] HENNESSY JL, UNPUB IEEE T COMPUT
  • [5] HOPKINS M, 1984, MAY P C HIGH LEV LAN
  • [6] HOPKINS M, 1983, 21ST P ANN IEEE COMP, P108
  • [7] KATEVENIS MGH, 1983, THESIS U CALIFORNIA
  • [8] EMPIRICAL EVALUATION OF SOME FEATURES OF INSTRUCTION SET PROCESSOR ARCHITECTURES
    LUNDE, A
    [J]. COMMUNICATIONS OF THE ACM, 1977, 20 (03) : 143 - 153
  • [9] Patterson D. A., 1984, Computer Architecture News, V12, P11, DOI 10.1145/641602.641604
  • [10] PATTERSON DA, 1982, COMPUTER, V15, P8, DOI 10.1109/MC.1982.1654133