A 10-B 20-MHZ 30-MW PIPELINED INTERPOLATING CMOS ADC

被引：67

作者：

KUSUMOTO, K

MATSUZAWA, A

MURATA, K

机构：

[1] VLSI Devices Research Laboratory, Semiconductor Research Center, Matsushita Electric Industrial Co., Osaka

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1993年 / 28卷 / 12期

关键词：

D O I：

10.1109/4.261992

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for portable audio-visual equipment. Two new circuit techniques, termed pipelined capacitive interpolation and error averaging circuits with capacitor networks, are developed. As a result, very low power dissipation of 30 mW at a low power-supply voltage of 2.5 V is attained at the conversion frequency of 20 MHz. Also, a good DNL of less than +/- 0.5 LSB and an acceptable signal-to-noise and distortion ratio of 55 dB are obtained for the input frequencies of 1 kHz and 1 MHz, respectively. The ADC is fabricated in 0.8-mum CMOS technology and occupies an area of 2.6 x 2.5 mm2.

引用

页码：1200 / 1206

页数：7