CIRCUIT PERFORMANCE OPTIMIZATION AND MODEL-FITTING BASED ON SIMULATED ANNEALING

被引:3
作者
DURBIN, F [1 ]
HAUSSY, J [1 ]
BERTHIAU, G [1 ]
SIARRY, P [1 ]
机构
[1] ECOLE CENT PARIS,ELECTR LAB,F-92295 CHATENAY MALABRY,FRANCE
关键词
D O I
10.1080/00207219208925797
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An efficient new method, based on the coupling between an enhanced simulated annealing algorithm and the SPICE-PAC 'open' circuit simulator, is proposed for minimizing objective functions describing circuit performance optimization problems or component model fitting to experimental data. To keep the number of objective function evaluations and CPU times to the lowest possible level, we focus our attention on two features: first, we build an original partitioning technique for splitting large n-dimensional problems; then we carefully study variables discretization, (which is necessary for applying the simulated annealing method to continuous problems). To illustrate the efficiency of our method, we show how to determine the 40 MOS transistor model parameters, through fitting the model to experimental data.
引用
收藏
页码:1267 / 1271
页数:5
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