A 34-NS 16-MB DRAM WITH CONTROLLABLE VOLTAGE DOWN-CONVERTER

被引:8
作者
HIDAKA, H [1 ]
ARIMOTO, K [1 ]
HIRAYAMA, K [1 ]
HAYASHIKOSHI, M [1 ]
ASAKURA, M [1 ]
TSUKUDE, M [1 ]
OISHI, T [1 ]
KAWAI, S [1 ]
SUMA, K [1 ]
KONISHI, Y [1 ]
TANAKA, K [1 ]
WAKAMIYA, W [1 ]
OHNO, Y [1 ]
FUJISHIMA, K [1 ]
机构
[1] MITSUBISHI ELECTR CO,KITA ITAMI WORKS,ITAMI,HYOGO 664,JAPAN
关键词
D O I
10.1109/4.142597
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 16-Mb DRAM with a RASBAR access time (t(RAC)) Of 34 ns and a column address access time (t(CAA)) of 15 ns has been developed. New circuit techniques to meet the requirements for high speed are implemented-a multidivided column address decoding scheme and a fully embedded sense-amplifier driving scheme. A low-power hybrid internal power supply voltage converter with an accelerated life-test function is also proposed and demonstrated. In addition, a new substrate engineering technology, a retrograded well structure formed by a megaelectronvolt ion-implantation process, provides a simple process sequence and high reliability in terms of soft-error and latch-up immunity. All of these process and circuit technologies contribute to the realization of a highly reliable, high-speed 16-Mb DRAM.
引用
收藏
页码:1020 / 1027
页数:8
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