HIGH-PERFORMANCE BICMOS 100K-GATE ARRAY

被引：10

作者：

GALLIA, JD

YEE, AL

CHAU, KK

WANG, IF

DAVIS, H

SWAMY, S

NGUYEN, VM

RUPAREL, KN

MOORE, K

CHAE, B

LEMONDS, CE

EYRES, P

YOSHINO, T

SHAH, AH

机构：

[1] VLSI Design Laboratory, Texas Instruments Incorporated, Dallas, TX

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1990年 / 25卷 / 01期

关键词：

D O I：

10.1109/4.50296

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

- A BiCMOS gate array in 0.8-μm technology has been developed with CMOS intrinsic gate delays of 100 ps plus 60 ps/fan-out and BiCMOS intrinsic delays of 200 ps with a 17-ps/fan-out drive factor. A compact base cell (750 μm2/gate) has been designed with full bipolar drive capability for the efficient layout of both primitive gates and large-arrayed macros, such as register files and multipliers. A 106K-gate array has been built on a 1.14-cm square chip with ECL I/O capability. The place and route in three levels of metal provide array utilization greater than 90 percent. The gate array was used to implement a 74K-gate filter design with testability features such as JTAG and two-phase scan. © 1990 IEEE

引用

页码：142 / 149

页数：8