A 30-MHZ HYBRID ANALOG DIGITAL CLOCK RECOVERY CIRCUIT IN 2-MU-M CMOS

被引：69

作者：

KIM, B ^{[1
]}

HELMAN, DN ^{[1
]}

GRAY, PR ^{[1
]}

机构：

[1] UNIV CALIF BERKELEY,DEPT ELECT ENGN & COMP SCI,BERKELEY,CA 94720

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1990年 / 25卷 / 06期

基金：

美国国家科学基金会;

关键词：

D O I：

10.1109/4.62166

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A high-speed hybrid clock recovery circuit composed of an analog phase-locked loop (PLL) and a digital PLL (DPLL) for disk drive applications is described. The chip operates at a maximum data rate of 33 MHz from a single 5-V power supply and achieves fast acquisition, a decode window of 94% of full window width, effective sampling jitter of 100-ps rms, and an effective input sampling rate of 1 GHz. The ring oscillator in the analog PLL shows a 62 ppm/°C temperature coefficient (TC) and 4.5%/V supply sensitivity of free-running frequency. The total power dissipation is about 600 mW and the active area is 30000 mil2 in a 2-μm single-poly double-metal n-well CMOS process. © 1990 IEEE

引用

页码：1385 / 1394

页数：10