HARMONIC DISTORTION CAUSED BY CAPACITORS IMPLEMENTED WITH MOSFET GATES

被引：40

作者：

BEHR, AT

SCHNEIDER, MC

NOCETI, S

MONTORO, CG

机构：

[1] Laboratorio de Instrumentacão Eletrônica, Universidade Federal de Santa Catarina, CEP 88049, Florianópolis, SC

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1992年 / 27卷 / 10期

关键词：

D O I：

10.1109/4.156456

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The capacitive gate structures available in digital-orientated CMOS processes are reviewed, with emphasis on their use as linear capacitors. It is shown that the voltage harmonic distortion in MOS gate capacitors biased in either accumulation or strong inversion is almost technology independent. Experimental and analytical results indicate that the total harmonic distortion in an adequately biased (2.5 V) gate capacitor can be kept low (THD < -40 dB for a 3-V voltage swing).

引用

页码：1470 / 1475

页数：6

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