CLEANING TECHNOLOGY FOR IMPROVED GATE OXIDE INTEGRITY

被引:15
作者
MEURIS, M
VERHAVERBEKE, S
MERTENS, PW
SCHMIDT, HF
HEYNS, MM
KUBOTA, M
PHILIPOSSIAN, A
DILLENBECK, K
GRAF, D
SCHNEGG, A
DEBLANK, R
机构
[1] IMEC, B-3001 Leuven
[2] Sony Corp., Atsugi-shi, Kanagawa-ken, Asahi-cho
[3] Digital Equipment Corporation, Hudson, MA 01749
[4] Ashland Chemical Inc., Columbus, OH 43216
[5] Wacker-Chemitronic, D-8263 Burghausen
[6] ASM International, 3723 BJ Bilthoven
关键词
D O I
10.1016/0167-9317(93)90123-M
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The effect of metal contamination and silicon surface defects on the gate oxide yield is investigated. The characteristics of various cleaning procedures are studied and correlated with the integrity of thin gate oxides. The standard wet cleaning recipe is optimized and a new cleaning strategy is proposed. Selective contamination experiments in chemicals are used to investigate the effect of small amounts of metal contaminants on the gate oxide integrity. HF-last processes are investigated and a new wet cleaning strategy is proposed.
引用
收藏
页码:21 / 28
页数:8
相关论文
共 9 条
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