HIGH-DENSITY ZERO SUPPRESSOR AND ENCODER VME BOARD USING FIELD-PROGRAMMABLE GATE ARRAY

被引：3

作者：

ALOISIO, A ^{[1
]}

CEVENINI, F ^{[1
]}

PATRICELLI, S ^{[1
]}

PARASCANDOLO, P ^{[1
]}

机构：

[1] INFN,SEZ NAPOLI,I-80125 NAPLES,ITALY

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 1994年 / 41卷 / 01期

关键词：

D O I：

10.1109/23.281494

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We describe a 96 bit zero-suppressor and encoder VME board designed for the RPC trigger system of the L3 Forward/Backward Muon detector at CERN. Running at 20 MHz clock frequency, the board processes the elementary 96 bit wide detector pattern in less than one microsecond, storing hit addresses in a FIFO array. Details of the board architecture - based on seven XELINX XC3020 LCAs - are presented and simulation and preliminary test results are briefly reported.

引用

页码：225 / 227

页数：3